1. Field of the Invention
The present invention relates to a thin film transistor and method of fabricating the same and, more specifically, to a bottom gate thin film transistor and method of fabricating the same having a channel region crystallized by a super grain silicon (SGS) crystallization method by forming a gate electrode and a gate insulating layer on an insulating substrate, forming an amorphous silicon layer on the gate insulating layer followed by forming a capping layer and a metal catalyst layer, performing heat treatment to crystallize the amorphous silicon layer into a polysilicon layer, and forming an etch stopper, source and drain regions and source and drain electrodes.
2. Description of the Related Art
In general, in the thin film transistor used for a display device, a semiconductor layer is formed by depositing amorphous silicon on a transparent substrate such as glass or quartz, dehydrogenating the amorphous silicon, ion-implanting impurities for forming a channel, and then crystallizing the amorphous silicon.
As a method of crystallizing the amorphous silicon into polysilicon, there are a solid phase crystallization method, an excimer laser crystallization method, a metal induced crystallization method and a metal induced lateral crystallization method. In the solid phase crystallization method, the amorphous silicon layer is annealed for several to several tens of hours at a temperature less than 700° C., i.e., a transition temperature of glass that forms a substrate of the display device in which the thin film transistor is used. In the excimer laser crystallization method, an excimer laser is irradiated onto a silicon layer so that the silicon layer is locally heated for a very short time at a high temperature to crystallize. In the metal induced crystallization method, metal such as Ni, Pd, Ag, or Al is in contact with or injected into the amorphous silicon layer so that a phenomenon that phase change of the amorphous silicon into the polysilicon is derived by the metal is used. In the metal induced lateral crystallization method, silicon is crystallized in a manner that silicide that is generated by reacting metal with silicon is laterally propagated to induce crystallization of the silicon.
FIGS. 1A and 1B are cross-sectional views illustrating a fabrication process of a conventional thin film transistor;
FIG. 1A is a cross-sectional view of a fabrication process of a top-gate thin film transistor. As shown in FIG. 1A, a buffer layer 12 is formed to prevent penetration of gas or moisture into an insulating substrate 11 such as glass or plastic, and an amorphous silicon layer is formed on the buffer layer 12.
After crystallizing the amorphous silicon layer by the aforementioned crystallization process, the amorphous silicon layer is patterned to form a semiconductor layer 13 having a polysilicon layer, and a gate insulating layer 14 is formed in a single or double layer of a silicon oxide layer or a silicon nitride layer.
A gate electrode 15 is then formed of a conductive material on the substrate, and an interlayer insulating layer 16 is formed of an insulating layer.
Next, a contact hole opening a predetermined region of the semiconductor layer is formed by etching a predetermined region of a gate insulating layer and the interlayer insulating layer, and then source and drain electrodes 17 are formed to complete the top-gate thin film transistor.
FIG. 1B is a cross-sectional view of a fabrication process of a bottom-gate thin film transistor. As shown in FIG. 1B, a buffer layer 22 is formed on an insulating substrate 21 such as glass or plastic, and a metal material is formed on the entire surface of the substrate and patterned to form a gate electrode 23.
Next, a gate insulating layer 24 is formed on the entire surface of the substrate in a single or double layer of a silicon oxide layer or a silicon nitride layer.
Next, an amorphous silicon layer is deposited on the entire surface of the substrate, and patterned to form an amorphous silicon layer pattern 25.
An insulating layer is then formed on the entire surface of the substrate and patterned to form an etch stopper 26 over a channel region of the amorphous silicon layer pattern 25.
Next, a highly doped amorphous silicon layer is formed on the entire surface of the substrate, and patterned using a photoresist pattern and the etch stopper, so that a highly doped amorphous silicon layer pattern 27 is formed to define source and drain regions.
Next, a conductive metal is deposited on the entire surface of the substrate and patterned using the photoresist pattern and the etch stopper to form source and drain electrodes 28, so that the bottom-gate thin film transistor is finally obtained.
The aforementioned top-gate thin film transistor has merits in that the semiconductor layer having the polysilicon layer is formed by various crystallization methods so that an on/off rate of the thin film transistor is fast and electron mobility is high. However, the top-gate thin film transistor has a drawback in that the fabrication process is complicated. Moreover, an interface between the gate insulating layer and the semiconductor layer is exposed so that it is susceptible to contamination or defects. On the contrary, the bottom gate thin film transistor has merits in that the fabrication process is simple and the interface between the gate insulating layer and the channel region is not exposed. However, the bottom gate thin film transistor has drawbacks in that the operating speed and electron mobility are low because the channel region is made of the amorphous silicon layer due to difficulty in crystallization.